This invention relates to the techniques for forming a specific pattern for a semiconductor integrated circuit, such as LSI, on a specimen, such as a mask or a wafer, using a charged beam at high speed with high accuracy, and more particularly to a method for generating exposure data for lithographic apparatus from the design data on the pattern.
This application is based on Japanese Patent Application No. 9-65149, filed Mar. 18, 1997, the content of which is incorporated herein by reference.
As semiconductor integrated circuits have been getting much larger and circuit elements have been getting much smaller, the techniques for forming a pattern on a wafer or a mask with an exposure device have been developed. To form a specific pattern on a wafer or a mask with an exposure device based on the LSI design pattern data generated through logic design, circuit design, and layout design, it is necessary to convert the design pattern data into exposure data that the exposure device can deal with.
In the process of converting the design data into the exposure data, when the design data has a multilayer cell structure, it is necessary to convert the multilayer cell structure into a single-layer cell structure, since the exposure data cannot have more than one layer for each mask or wafer. To prevent a decrease in the writing accuracy due to multiple exposure caused by the overlapping of patterns, the overlapping removal of patterns should be performed. Also the following processes are performed in general: the size correction to enlarge or reduce the design data, and the division of the corrected patterns into patterns of basic unit shapes that the exposure device can print.
In the design data, LSI patterns are defined on layers. The multiple layers of pattern data defined in the design data are subjected to Boolean shape data operations, such as AND, OR, EXOR, or NOT operation to create pattern data defined by a single layer that can be inputted to an exposure device. This method has been used frequently.
In recent years, the techniques for compressing exposure data in converting design data into exposure data to reduce the amount of exposure data transferred to an exposure device have been proposed. One technique has been disclosed in Japanese Patent Disclosure (KOKAI) No. 5-29202. The disclosed technique is to divide a pattern (the shaded portion indicates the exposure section) as shown in FIG. 1 into subfields in an electron beam exposure device to produce unit shapes, acquire information on the arrangement of unit shapes, and compress the amount of data.
This type of conventional technique has the following problem. The time required to convert design data into exposure data increases, because unit shapes for data compression are generated after the design data is exploded on the entire surface of a specimen and then is divided into grid-like subfields peculiar to an exposure device and further because information on the arrangement of unit shapes is acquired. Since unit shapes are generated in subfields, the pattern of an odd portion smaller than a subfield cannot be compressed using unit shapes. This causes the problem of not compressing the amount of data so much as the data conversion time increases.
For the techniques for shortening the data conversion time and compressing the amount of data, a hierarchical data conversion method making use of a cell hierarchical structure in the design data has been proposed.
The hierarchical data conversion method has been described in, for example, "High-speed Electron Beam Data Conversion System Combining Hierarchical Operation with Parallel Processing," Japanese Journal of Applied Physics Volume 31, pp. 4257-4261, 1992 (hereinafter, referred to as reference 1). In reference 1, if the hierarchical data conversion method is naively applied to original CAD data to produce exposure data, there is a chance that double-exposed exposure patterns or exposure pattern with a gap between them may be generated. As a result, such exposure data may not be accepted by an electron beam exposure device. To overcome this problem, the following approach has been proposed in reference 1: when cells overlap at least partially in the design data, the cells are expanded into the parent cell which refers those cells at one level higher in the hierarchy (hereinafter, such an expansion is referred to as explosion) (removal of overlapping cells) to change the hierarchical structure and the resulting design data is subjected to a hierarchical shape data operation, thereby converting the design data into the pattern data for an electron beam exposure device properly. Hereinafter, the process of changing the hierarchical structure, such as removal of overlapping cells, needed in converting the design data hierarchically into writing pattern data is referred as the hierarchical optimization process.
When master cells which are referred, 2-to plural times in the design data are exploded, the removal of overlapping cells causes the problem of decreasing the efficiency in shortening the processing time by the hierarchical processing and the efficiency in compressing the amount of data. Specifically, when the array of a cell overlaps with a single shape or with another cell in the design data, or when the arrays of different cells overlap, the efficiency in shortening the processing time by the hierarchical process and the data-amount compression efficiency decreases.
One approach to solve this problem has been described in "New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion," Proceedings of 27th ACM/IEEE Design Automation Conference, pp. 321-326, 1990 (hereinafter, referred to as reference 2). In reference 2, when cells overlap in a hierarchical shape data operation process, objects of cell explosion are limited to overlaps between cells more than one level apart in the hierarchy. Stated another way, if the cell overlaps the other cell whose level in a hierarchical tree is upper or lower by only one level than that of the cell, the cell is not exploded into the cell at a higher level hierarchy. Instead, the shapes overlapping between cells are attached marks and subjected to suitable shape data operations, thereby increasing the efficiency of the hierarchical process remarkably.
Any of the above conventional techniques, however, has not disclosed a method of suppressing cell explosion in the case of the overlapping of cells in array arrangement contributing to the most serious decrease in the efficiency of the hierarchical process. Additionally, it has not disclosed a method of avoiding cell explosion as much as possible and hierarchically converting the design data properly, when shape data operations are performed on more than one layer of the design data.